Lead Lag Pole (Z-Domain)

This function simulates a lead-lag pole function in the discrete domain. The component is triggered by the 2-element, interpolated Enable/Disable port signal. The user has the ability to reset the output to a user-specified value at any executed instance. If the Reset signal is received between two execution steps, the output will be reset at the next execution step.

Input Parameters

Name for Identification	Text		Optional text parameter for identification of the component.

Fortran Comment	Text		An optional Fortran comment. The text entered here is included in the project Fortran file

Limit Output?	Choice		Select Yes or No to enable or disable non-windup limits.

Resettable?	Choice		Select Never, Anytime or Timezero. When to enable reset. If Anytime is selected, a port for the reset signal is enabled.

Reset Value	Real	Variable	Value output upon reset action.

Is Input Already Sampled?	Choice		Select Yes if the input to the component is already executed at the same execution signal. If No is selected, the input will be re-sampled before execution.

Dimension	Integer	Literal	Enter the dimension of the input signal. The output will be of the same dimension.

Gain	Real	Variable	Gain factor.

Lead Time Constant	Real	Variable	Lead Time constant (T1) [s].

Lag Time Constant	Real	Variable	Lag Time constant (T2) [s].

	Output signal
	Time at last execution
	Time at execution, before the last execution
	Input signal at last execution
	Output generated at execution, before the last execution
	Gain at last execution
	Lead time constant at last execution
	Lag time constant at last execution

Lead-Lag Pole (Z-Domain)

Description

Input Parameters

Maximum Limit	Real	Variable	Maximum limit of the lead-lag pole, visible only if Limit Output? \| Yes is selected.

Minimum Limit	Real	Variable	Minimum limit of the lead-lag pole, visible only if Limit Output? \| Yes is selected.