This component models standard binary logic gates. Non-zero values are interpreted as logical true values, while zero is interpreted as a logical false. This component will output the value 1 for a logical true, and 0 for a logical false, depending on the logic state of the inputs:
AND: Outputs logical true if and only if all inputs receive a logical true.
OR: Outputs logical true if any of its inputs receive a logical true.
XOR: XOR is determined by the Fortran logical non-equivalence (.NEQV.) operator.
This component allows up to 9 inputs per gate. The user may invert any input as well as the output at their discretion.
If Interpolation Compatibility is enabled, then the interpolated information is passed to the device output based on the relevant logic truth table (i.e. AND, OR or XOR) and the exact instants in which the inputs transition. When full interpolation is utilized, this device is very accurate even at larger time steps.
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