Phase Locked Loop (PLL)

 

Description

This component is a 3-phase, p-controlled phase locked loop, which generates a ramp signal theta that varies between 0 and 360°, synchronized or locked in phase, to the input voltage Va.

 

The Phase Vector Technique is used to generate the signal theta. This technique exploits trigonometric multiplication identities to form an error signal that speeds up and slows down the phase-locked oscillator, to match the phase of the input. The phase error (in degrees), as well as the tracked frequency of the input voltage can both be returned as an internal output variables.

Block Diagram

The figure below illustrates the block diagram of the phase-locked loop:

 

 

Input signals Va, Vb and Vc are the per-unitized, instantaneous voltage of a three-phase electrical system. Gp and Gi are the proportional gain and integral gain respectively. The Park transformation is expressed in matrix form, as shown below. Function tan-1(Vq/Vd) returns the phase angle of the complex number Vd + jVq.

 

 

More:

Knowledge Base Article

Input Parameters

ConfigurationConfiguration

 

Name for Identification

 

Text

 

Enter an optional name for this component instance.

 

 

 

 

 

 Proportional Gain

 

REAL

Variable

Proportional gain factor

 

 

 

 

 

Integral Gain

 

REAL

Variable

Integral gain factor

 

 

 

 

 

Base Volts

 

REAL

Constant

System base voltage [V]

 

 

 

 

 

Base Frequency

 

REAL

Constant

System base frequency [Hz]

 

 

 

 

 

Number of Outputs

 

Choice

 

Select an array of 1, 6 or 12 for output to theta

 

 

 

 

 

Angle Input/Output Mode

 

Choice

 

Select Radians or Degrees

 

 

 

 

 

Offset Angle to PLL (rad/deg as per  Pmode)

 

REAL

Variable

The initial offset or 'phase shift' of the PLL output waveform. This value should be input in radians or degrees, according to Angle Input/Output Mode setting [rad] [°]

 

 

 

 

 

PLL Shadows err for t < TREL

 

REAL

Variable

Similar to an initialization time. During this time, the output will be the error signal of the phase locked loop [s]

 

 

 

 

 

Delta Ramps Lead or Lag Wye Ramps

 

Choice

 

Select Lead or Lag. The selection depends on the connection setting of the Delta winding (i.e. whether it is leading or lagging the Wye winding).

 

This parameter is enabled only Number of Outputs | n=12  is selected.

 

 

 

 

 

Upper Tracking Limit

 

REAL

Variable

Upper boundary for tracked frequency as a per unit value of base frequency. This should be greater than 1.0. If the value is not greater than 1.0, then a value of 1.2 is assumed.

 

 

 

 

 

Lower Tracking Limit

 

REAL

Variable

Lower boundary for tracked frequency as a per unit value of base frequency. This should be between 0.0 and 1.0. If the value is outside this range, then a value of 0.8 is assumed.

 

Internal Output VariablesInternal Output Variables

 

 Name for Tracked Frequency

 

REAL

Output

Enter a name to monitor the tracked frequency [rad/s]

 

 

 

 

 

Name for Error

 

REAL

Output

Enter a name to monitor the error signal [°]