The Hysteresis Buffer is an ideal component for converting a real signal into a logic one. The hysteresis function provides some noise immunity by preventing a transition to a new logic state until the input signal has moved decidedly across the input threshold. While the input signal is inside the hysteresis region, the previous output level is maintained.
If Interpolation Compatibility is enabled, then interpolated information is generated by the device and sent to the output. The output interpolated time is calculated by continuously monitoring the input signal, and comparing it to the Logic 1 and Logic 0 Input Levels. When the input signal crosses either input level, an interpolated time is given. When full interpolation is utilized, this device is very accurate even at larger time steps.
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Name for Identification |
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Optional text parameter for identification of the component. |
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Logic 1 Input Level |
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REAL |
Variable |
The level the input signal must exceed to be considered a logical true value |
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Logic 0 Input Level |
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REAL |
Variable |
The level below which the input signal must be before considered a logical false |
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Invert Output |
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Choice |
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Select Yes or No |
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Interpolation Compatibility |
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Choice |
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Select Disable or Enable. See Description for more details. |