This component represents one of four flip-flop/latch configurations: JK, SR, D and T.
The main difference between a latch and a flip-flop is that for a latch, its output is constantly affected by its inputs, as long as the enable signal E is asserted. In other words, when enabled, latch outputs change immediately when the signals inputs change. The output state of flip-flops, on the other hand, change depending on the value of the clock input C. If C is chosen as falling, the output changes state only on the falling edge of a clock pulse. If it is chosen as rising, the output changes state only on the rising edge of a clock pulse. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
This component can be configured as one of three modes of operation:
If Interpolation Compatibility is enabled, then the relevant interpolated information, from either the inputs or the clock, is passed to the device outputs Q and Qbar. In addition, the interpolated information is used to determine the flip-flop logic according to the exact instants in which the inputs and the clock signals transition. When full interpolation is utilized, this device is very accurate even at larger time steps.
For descriptions of the four flip-flop configurations, see below.
More: |
When configured as a JK flip-flop, this component possesses the following properties and truth table:
J |
K |
Q(n)
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Qbar(n)
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0 |
0 |
Q(n-1) |
Qbar(n-1) |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1- Q(n-1) |
1 - Qbar(n-1) |
The state, in which both J and K are 1, is an undesirable state for this type of flip-flop under normal conditions, as the output will continue complementing until the clock pulse returns to 0. Q(n) and Qbar(n) are the present states. Q(n-1) and Qbar(n-1) correspond to the states prior to the latest transition.
When configured as a SR flip-flop, this component possesses the following properties and truth table:
S |
R |
Q(n)
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Qbar(n)
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0 |
0 |
Q(n-1) |
Qbar(n-1) |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
Q(n-1) |
Qbar(n-1) |
The state, in which both R and S are 1, is an undesirable state for this flip-flop under normal conditions, as the output will continue complementing until the clock pulse returns to 0. Q(n) and Qbar(n) are the present states. Q(n-1) and Qbar(n-1) correspond to the states prior to the latest transition.
When configured as a D flip-flop, this component possesses the following properties and truth table:
D |
Q(n)
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Qbar(n)
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0 |
0 |
1 |
1 |
1 |
0 |
Q(n) and Qbar(n) represent the current state (i.e. correspond to the current inputs).
When configured as a D flip-flop, this component possesses the following properties and truth table:
T |
Q(n)
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Qbar(n)
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0 |
Q(n-1) |
Qbar(n-1) |
1 |
1 - Q(n-1) |
1 - Qbar(n-1) |
Q(n) and Qbar(n) represent the current state (i.e. correspond to the current inputs).
Name for Identification |
Text |
Optional text parameter for identification of the component. |
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Flip-Flop, Gated Latch or Latch |
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Choice |
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Select Flip-flop, Gated Latch, or Simple Set/Reset Latch. |
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Flip-Flop Type |
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Choice |
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Select JK, RS, D or T. |
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Initial State of Output Q |
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Choice |
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Select Low [0] or High [1]. This is the initial state of output Q at time zero. |
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Active Clock Trigger Edge |
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Choice |
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Select Negative [1->0] or Positive [0->1]. This input indicates what part of the clock signal will be used to activate a flip-flop transition. These are falling and rising edge respectively.
This parameter is enabled only while in Flip-Flop mode. |
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Interpolation Compatibility |
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Choice |
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Select Disabled or Enabled. See Description for more details. |